RXFE=NOERROR, THRE=VALIDDATA, PE=INACTIVE, BI=INACTIVE, RDR=EMPTY, TEMT=VALIDDATA, OE=INACTIVE, FE=INACTIVE
Line Status Register. Contains flags for transmit and receive status, including line errors.
| RDR | Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty. 0 (EMPTY): The UARTn receiver FIFO is empty. 1 (NOTEMPTY): The UARTn receiver FIFO is not empty. |
| OE | Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost. 0 (INACTIVE): Overrun error status is inactive. 1 (ACTIVE): Overrun error status is active. |
| PE | Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO. 0 (INACTIVE): Parity error status is inactive. 1 (ACTIVE): Parity error status is active. |
| FE | Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO. 0 (INACTIVE): Framing error status is inactive. 1 (ACTIVE): Framing error status is active. |
| BI | Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO. 0 (INACTIVE): Break interrupt status is inactive. 1 (ACTIVE): Break interrupt status is active. |
| THRE | Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write. 0 (VALIDDATA): UnTHR contains valid data. 1 (EMPTY): UnTHR is empty. |
| TEMT | Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data. 0 (VALIDDATA): UnTHR and/or the UnTSR contains valid data. 1 (EMPTY): UnTHR and the UnTSR are empty. |
| RXFE | Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO. 0 (NOERROR): UnRBR contains no UARTn RX errors or UnFCR[0]=0. 1 (ERRORS): UARTn RBR contains at least one UARTn RX error. |
| RESERVED | Reserved. The value read from a reserved bit is not defined. |